// *********************************************************************************
// Project Name : zkx2024
// Author       : Glqu
// Email        : QGL_MAX@163.com
// Create Time  : 2024-05-02
// File Name    : rd_sram_ctrl.v
// Module Name  : rd_sram_ctrl
// Called By    :
// Abstract     :
//
// 
// *********************************************************************************
// Modification History:
// Date         By              Version                 Change Description
// -----------------------------------------------------------------------
// 2024-05-02    Macro           1.0                     Original
//  
// *********************************************************************************
module rd_sram_ctrl(
    input RD_EN_0,
    input RD_EN_1,
    input RD_EN_2,
    input RD_EN_3,
    input RD_EN_4,
    input RD_EN_5,
    input RD_EN_6,
    input RD_EN_7,
    input RD_EN_8,
    input RD_EN_9,
    input RD_EN_10,
    input RD_EN_11,
    input RD_EN_12,
    input RD_EN_13,
    input RD_EN_14,
    input RD_EN_15,

    input [4:0] SRAM_NUM_0,
    input [4:0] SRAM_NUM_1,
    input [4:0] SRAM_NUM_2,
    input [4:0] SRAM_NUM_3,
    input [4:0] SRAM_NUM_4,
    input [4:0] SRAM_NUM_5,
    input [4:0] SRAM_NUM_6,
    input [4:0] SRAM_NUM_7,
    input [4:0] SRAM_NUM_8,
    input [4:0] SRAM_NUM_9,
    input [4:0] SRAM_NUM_10,
    input [4:0] SRAM_NUM_11,
    input [4:0] SRAM_NUM_12,
    input [4:0] SRAM_NUM_13,
    input [4:0] SRAM_NUM_14,
    input [4:0] SRAM_NUM_15,

    input [12:0] ADDR_0,
    input [12:0] ADDR_1,
    input [12:0] ADDR_2,
    input [12:0] ADDR_3,
    input [12:0] ADDR_4,
    input [12:0] ADDR_5,
    input [12:0] ADDR_6,
    input [12:0] ADDR_7,
    input [12:0] ADDR_8,
    input [12:0] ADDR_9,
    input [12:0] ADDR_10,
    input [12:0] ADDR_11,
    input [12:0] ADDR_12,
    input [12:0] ADDR_13,
    input [12:0] ADDR_14,
    input [12:0] ADDR_15,

    output reg [12:0] ADDR_O,
    output reg RD
);

parameter RD_SRAM_num=5'd0;

assign RD=  (SRAM_NUM_0==RD_SRAM_num)&&RD_EN_0 ||
            (SRAM_NUM_1==RD_SRAM_num)&&RD_EN_1 ||
            (SRAM_NUM_2==RD_SRAM_num)&&RD_EN_2 ||
            (SRAM_NUM_3==RD_SRAM_num)&&RD_EN_3 ||
            (SRAM_NUM_4==RD_SRAM_num)&&RD_EN_4 ||
            (SRAM_NUM_5==RD_SRAM_num)&&RD_EN_5 ||
            (SRAM_NUM_6==RD_SRAM_num)&&RD_EN_6 ||
            (SRAM_NUM_7==RD_SRAM_num)&&RD_EN_7 ||
            (SRAM_NUM_8==RD_SRAM_num)&&RD_EN_8 ||
            (SRAM_NUM_9==RD_SRAM_num)&&RD_EN_9 ||
            (SRAM_NUM_10==RD_SRAM_num)&&RD_EN_10 ||
            (SRAM_NUM_11==RD_SRAM_num)&&RD_EN_11 ||
            (SRAM_NUM_12==RD_SRAM_num)&&RD_EN_12 ||
            (SRAM_NUM_13==RD_SRAM_num)&&RD_EN_13 ||
            (SRAM_NUM_14==RD_SRAM_num)&&RD_EN_14 ||
            (SRAM_NUM_15==RD_SRAM_num)&&RD_EN_15;

assign ADDR_O=  ({13{((SRAM_NUM_0==RD_SRAM_num)&&RD_EN_0)}}&ADDR_0) |
                ({13{((SRAM_NUM_1==RD_SRAM_num)&&RD_EN_1)}}&ADDR_1) |
                ({13{((SRAM_NUM_2==RD_SRAM_num)&&RD_EN_2)}}&ADDR_2) |
                ({13{((SRAM_NUM_3==RD_SRAM_num)&&RD_EN_3)}}&ADDR_3) |
                ({13{((SRAM_NUM_4==RD_SRAM_num)&&RD_EN_4)}}&ADDR_4) |
                ({13{((SRAM_NUM_5==RD_SRAM_num)&&RD_EN_5)}}&ADDR_5) |
                ({13{((SRAM_NUM_6==RD_SRAM_num)&&RD_EN_6)}}&ADDR_6) |
                ({13{((SRAM_NUM_7==RD_SRAM_num)&&RD_EN_7)}}&ADDR_7) |
                ({13{((SRAM_NUM_8==RD_SRAM_num)&&RD_EN_8)}}&ADDR_8) |
                ({13{((SRAM_NUM_9==RD_SRAM_num)&&RD_EN_9)}}&ADDR_9) |
                ({13{((SRAM_NUM_10==RD_SRAM_num)&&RD_EN_10)}}&ADDR_10) |
                ({13{((SRAM_NUM_11==RD_SRAM_num)&&RD_EN_11)}}&ADDR_11) |
                ({13{((SRAM_NUM_12==RD_SRAM_num)&&RD_EN_12)}}&ADDR_12) |
                ({13{((SRAM_NUM_13==RD_SRAM_num)&&RD_EN_13)}}&ADDR_13) |
                ({13{((SRAM_NUM_14==RD_SRAM_num)&&RD_EN_14)}}&ADDR_14) |
                ({13{((SRAM_NUM_15==RD_SRAM_num)&&RD_EN_15)}}&ADDR_15);

endmodule

